====== Switch-on delay ======

{{:en:mervis-ide:35-help:bd12.png}}

===== Block name =====

BD12_SWITCHONDELAY

===== ST call =====

<code st-iec>
PROGRAM BD12_TEST
VAR 
  IN1,OUT1: BOOL;
 FB: LIB.CORE.V1_1.BD12_SWITCHONDELAY;
END_VAR
    FB(IN:=IN1);
    OUT1:=FB.OUT;
END_PROGRAM
</code>

===== Library =====

LIB\CORE

===== Version =====

V1.1

===== Description =====

The delay block transforms the input signal //IN// so that each rising edge is delayed by //TON//. The falling edge of //IN// is not delayed, it appears on the output immediately. The //TRES// parameter gives time remaining to the end of delay. The //TRES// value can be reset by a rising edge on the //RESET// input.

{{:en:mervis-ide:35-help:bd12_1.png}}

===== Inputs =====

|Input          |Type|Description                                         |Default value|
|IN             |BOOL|Input value                                         |False        |
|RESET          |BOOL|Resets the //TRES//                                 |False        |
|IGNORESTARTEDGE|BOOL|If //TRUE// the block is not initialised after start|False        |
|TON            |TIME|Rising edge delay (30 s by default).                |30s          |

===== Outputs =====

|Output|Type|Description                       |
|OUT   |BOOL|Output signal                     |
|TRES  |TIME|Time remaining to the end of delay|

===== Application example =====

{{:en:mervis-ide:35-help:bd12_example.png}}\\


The usage of this block is very versatile, in fact, this is one of the most used blocks at all. It is used for time insensivity of binary alarms, for sequential switching of cascade members, or for time delays at AHU starting sequence.

\\


===== Older versions  =====

\\


Version V1.0 is flagged as BROKEN. It contained an error of IGNORESTARTEDGE input. Valu on this input during firt cycle of program was not reflecter even if the function block was set correctly.